diff --git a/board/tqc/tqm85xx/tlb.c b/board/tqc/tqm85xx/tlb.c
index 7f4efc1..380448a 100644
--- a/board/tqc/tqm85xx/tlb.c
+++ b/board/tqc/tqm85xx/tlb.c
@@ -44,6 +44,7 @@
 		       MAS3_SX | MAS3_SW | MAS3_SR, 0,
 		       0, 0, BOOKE_PAGESZ_4K, 0),
 
+#ifndef CONFIG_TQM_BIGFLASH
 	/*
 	 * TLB 0, 1:	128M	Non-cacheable, guarded
 	 * 0xf8000000	128M	FLASH
@@ -146,6 +147,102 @@
 		       0, 9, BOOKE_PAGESZ_16M, 1),
 #endif /* CONFIG_PCIE */
 
+#else /* CONFIG_TQM_BIGFLASH */
+
+	/*
+	 * TLB 0,1,2,3:	  1G	Non-cacheable, guarded
+	 * 0xc0000000	  1G	FLASH
+	 * Out of reset this entry is only 4K.
+	 */
+	SET_TLB_ENTRY (1, CFG_FLASH_BASE, CFG_FLASH_BASE,
+		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+		       0, 3, BOOKE_PAGESZ_256M, 1),
+	SET_TLB_ENTRY (1, CFG_FLASH_BASE + 0x10000000,
+		       CFG_FLASH_BASE + 0x10000000,
+		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+		       0, 2, BOOKE_PAGESZ_256M, 1),
+	SET_TLB_ENTRY (1, CFG_FLASH_BASE + 0x20000000,
+		       CFG_FLASH_BASE + 0x20000000,
+		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+		       0, 1, BOOKE_PAGESZ_256M, 1),
+	SET_TLB_ENTRY (1, CFG_FLASH_BASE + 0x30000000,
+		       CFG_FLASH_BASE + 0x30000000,
+		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+		       0, 0, BOOKE_PAGESZ_256M, 1),
+
+	/*
+	 * TLB 4:	256M	Non-cacheable, guarded
+	 * 0x80000000	256M	PCI1 MEM First half
+	 */
+	SET_TLB_ENTRY (1, CFG_PCI1_MEM_PHYS, CFG_PCI1_MEM_PHYS,
+		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+		       0, 4, BOOKE_PAGESZ_256M, 1),
+
+	/*
+	 * TLB 5:	256M	Non-cacheable, guarded
+	 * 0x90000000	256M	PCI1 MEM Second half
+	 */
+	SET_TLB_ENTRY (1, CFG_PCI1_MEM_PHYS + 0x10000000,
+		       CFG_PCI1_MEM_PHYS + 0x10000000,
+		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+		       0, 5, BOOKE_PAGESZ_256M, 1),
+
+#ifdef CONFIG_PCIE1
+	/*
+	 * TLB 6:	256M	Non-cacheable, guarded
+	 * 0xc0000000	256M	PCI express MEM First half
+	 */
+	SET_TLB_ENTRY (1, CFG_PCIE1_MEM_BASE, CFG_PCIE1_MEM_BASE,
+		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+		       0, 6, BOOKE_PAGESZ_256M, 1),
+#else /* !CONFIG_PCIE */
+	/*
+	 * TLB 6:	256M	Non-cacheable, guarded
+	 * 0xb0000000	256M	Rapid IO MEM First half
+	 */
+	SET_TLB_ENTRY (1, CFG_RIO_MEM_BASE, CFG_RIO_MEM_BASE,
+		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+		       0, 6, BOOKE_PAGESZ_256M, 1),
+
+#endif /* CONFIG_PCIE */
+
+	/*
+	 * TLB 7:	 64M	Non-cacheable, guarded
+	 * 0xa0000000	  1M	CCSRBAR
+	 * 0xa2000000	 16M	PCI1 IO
+	 * 0xa3000000	 16M	CAN and NAND Flash
+	 */
+	SET_TLB_ENTRY (1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS,
+		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+		       0, 7, BOOKE_PAGESZ_64M, 1),
+
+	/*
+	 * TLB 8+9:	512M	 DDR, cache disabled (needed for memory test)
+	 * 0x00000000	512M	 DDR System memory
+	 * Without SPD EEPROM configured DDR, this must be setup manually.
+	 * Make sure the TLB count at the top of this table is correct.
+	 * Likely it needs to be increased by two for these entries.
+	 */
+	SET_TLB_ENTRY (1, CFG_DDR_SDRAM_BASE, CFG_DDR_SDRAM_BASE,
+		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+		       0, 8, BOOKE_PAGESZ_256M, 1),
+
+	SET_TLB_ENTRY (1, CFG_DDR_SDRAM_BASE + 0x10000000,
+		       CFG_DDR_SDRAM_BASE + 0x10000000,
+		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+		       0, 9, BOOKE_PAGESZ_256M, 1),
+
+#ifdef CONFIG_PCIE1
+	/*
+	 * TLB 10:	 16M	Non-cacheable, guarded
+	 * 0xaf000000	 16M	PCI express IO
+	 */
+	SET_TLB_ENTRY (1, CFG_PCIE1_IO_BASE, CFG_PCIE1_IO_BASE,
+		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
+		       0, 10, BOOKE_PAGESZ_16M, 1),
+#endif /* CONFIG_PCIE */
+
+#endif /* CONFIG_TQM_BIGFLASH */
 };
 
 int num_tlb_entries = ARRAY_SIZE (tlb_table);